Operating frequencies and integration densities are technical factors that may influence the cost of semiconductor devices. Device manufacturers are generally concerned with enhancing device performance and factors that affect the commercial value of the devices. As the operating frequency (or speed) is mostly affected by the resistance of interconnections connecting electrodes of transistors to each other in circuit patterns, it may be desirable to reduce the resistance of interconnections and to use techniques to improve operation and/or integration characteristics. Considering that the resistance of interconnections is dependent on the resistivity and sectional area of a material used for the interconnections, there has been proposed a technique for forming interconnections using a low-resistivity material, such as aluminum (Al) or copper (Cu). The Cu damascene process is a typical technique used to reduce interconnection resistance.
On the other hand, a shrink-down of pitches on conductive patterns, including interconnections, may be used to enhance the integration density of a semiconductor device. However, such a shrink-down in pitches of interconnections may cause the sheet resistance of the interconnections to increase. Such interconnections may use barrier metal layers to reduce the likelihood of an abnormal reaction and a diffusion of impurities.
FIG. 1 is a cross-section diagram that illustrates a conventional process for forming a semiconductor device that includes interconnection structures. In FIG. 1, a domain C1 depicts a partial section of a cell array region taken along a first direction, while a domain C2 depicts a vertical section of the domain C1 taken on a plane a.
Referring to FIG. 1, a field isolation layer 20 is formed in predetermined regions of a semiconductor substrate 10 to define active regions. The semiconductor substrate 10 may be divided into a cell array region and a peripheral region. After depositing a gate insulation layer 32 and a gate conductive layer 34 in sequence on the active regions, those layers 32 and 34 are patterned to form a gate pattern 30. From an ion implantation process with the gate pattern 30 as a mask, impurity regions 40 are provided in the active regions.
On the resultant structure where the impurity regions 40 are formed, an inter-level insulation layer 50 is deposited. The inter-level insulation layer 50 is patterned to form a first contact hole 55 partially opening the impurity regions of the cell array region. The impurity regions 50 exposed by the first contact hole 55 will be connected to a bitline formed by the subsequent process. After depositing a plug conductive layer on the inter-level insulation layer and filling the first contact hole 55, the plug conductive layer is etched away until the top surface of the inter-level insulation layer 50 is exposed. As a result, a contact plug 60 is formed that is connected to the impurity region 40 through the first contact hole 55. The contact plug 60 may be made of polycrystalline silicon.
A barrier metal layer 92 and a metal layer 94 are deposited on the inter-level insulation layer 50 in sequence. The metal layer 94 and the barrier metal layer 92 are patterned to form interconnecting constructions 90 connected to the contact plugs 60. During this, to prevent short circuits among the interconnecting constructions 90, the patterning process for the interconnecting constructions 90 is carried out with an over-etching technique. As a result of the over-etching, the inter-level insulation layer 50 around the interconnecting construction 90 becomes lower than the bottom of the barrier metal layer 92.
During the over-etching process, the contact plug 60 may not be etched anisotropically or removed faster than the inter-level insulation layer 50. As a result, as shown in FIG. 1, the top sides of the contact plug 60 may be etched away to result in a narrower section thereof, which causes the contact plug 60 not to be connected to the bitline 90 or to remain with high resistance.
In addition, the metal layer 94 is usually formed of aluminum, tungsten, or copper for high conductivity. But, when the metal layer 94 directly contacts the impurity regions 40 or the contact plug 60 that contains silicon, it may cause the degradation of quality due to impurity diffusion and abnormal reactions between the metal and the silicon. The barrier metal layer 92 is provided over a critical thickness tc to reduce the likelihood of such problems arising from contact between the metal and the silicon. However, the necessity for the critical thickness of the barrier metal layer 92 may reduce the ratio of an effective sectional area of the metal in the interconnecting construction 90, which may cause an abrupt increase of the sheet resistance in the interconnecting construction 90. Especially, if the minimum pitch of the interconnecting construction 90 is reduced to less than 0.1 μm, then the increase of the sheet resistance may be an important issue to address in fabricating high-frequency semiconductor devices.